1. The Field of the Invention
This invention relates generally to the field of bonding stacked silicon and glass wafers. In particular, exemplary embodiments of the present invention relate to improved devices and methods of anodically bonding multiple wafers or layers, and, more specifically, to methods of forming vias between the layers.
2. The Relevant Technology
Anodic bonding, also known as field assisted glass-silicon sealing, is a process which permits the sealing of silicon to glass at a temperature below the melting point of glass. The silicon and glass pieces, wafers, layers, or substrates are heated by an electrical device to about 400-500 degrees Celsius (° C.). FIG. 1 illustrates one general system that can be used to anodically bond silicon and glass pieces, wafers, layers, or substrates. The electrical device, such as a voltage source 105, applies a voltage across the wafers on the order of mid to high 100s of volts to heat up the wafers to the required temperature. Generally, a positive terminal 106 of the electrical device is connected to an anode, such as aluminum plate 125, located on or below a silicon wafer 120. Likewise, negative terminal 108 of the electrical device is connected to a cathode 110 located on or above a glass wafer 115. After applying voltage across the wafers one time, the silicon and glass are bonded together and can be cooled to room temperature.
This type of bonding is thought to be the result of mobile ions in the glass wafer. At higher temperatures, the negative ions on cathode 110 attract the positive sodium ions (Na+), causing the sodium ions to travel towards the cathode end of glass wafer 115. The remaining negative ions in glass wafer 115 form a space charge on the side of glass wafer 115 adjacent to silicon wafer 120. This generates an electric field, which pulls silicon wafer 120 and glass wafer 115 together during the process. Therefore, while the voltage is applied across the wafers and the temperature is raised, an electric field pulls the wafers together. After removing the voltage, the wafers are irreversibly chemically bonded together. The force of the electric field that pulls the wafers together is given by the equation F=E/d, where E is the electric field and d is the distance or gap between the wafers. Therefore, the smaller the gap between the wafers, the greater the force generated by the electric field. This provides incentive to make the surfaces as smooth and parallel as possible, in order to achieve the maximum force for a given electric field strength.
One way to think about anodic bonding is that the silicon-oxygen (Si—O) surface bonds must be broken and reformed through contact with the other wafer. This is a relatively strong bond (approximately 560 kcal/mole), which means that a large amount of energy is required to break these bonds. This energy can come from an elevated temperature and/or application of an electric field to the multilayer or wafer structure. The best way to increase the energy of the electric field is to decrease the separation between the wafers, i.e. decrease the distance in the force equation, through having low surface roughness Ra and very good planarity. In one embodiment, the surface roughness can be less than about 2 nm average roughness. There are many descriptions or definitions of surface roughness that can be used. One common description or definition that corresponds closely to what one would intuitively think by feeling a surface with the hand can be defined as Ra=(1/L)∫0L|z(x)−zave|dx, where z(x) represents the surface height at a given point, and zave is the average surface height. Thus, Ra is the integrated absolute deviation from the mean surface height within a region (0, L). Our sense of roughness, therefore, is closely modeled by absolute mean deviations rather than mean squared deviations for instance.
In addition to the problems with obtaining low surface roughness, a problem with existing processes is the necessity to use a high voltage and high temperatures to bond the wafers. Temperature and voltage can be generally independently controlled. The relationship between temperatures and voltage lies in the drifting of the ions being faster at higher temperatures and also faster at higher voltages. The temperature and voltage required for this process can cause extensive damage to pre-fabricated printed circuit boards (PCBs). Therefore, using prior art processes, it is not possible to create an anodic bond between a glass wafer and a fully-functional silicon PCB that includes sensitive electrical components without causing significant damage to the electrical interconnects and components residing on the PCB.
In an effort to minimize space in an electrical circuit, it is often advantageous to stack boards on top of one another with interposer wafers between them. If the current anodic bonding process is used, only a single silicon wafer can be bonded with a glass wafer because the electrical components and interconnects must be added after the anodic bonding process is complete. In contrast, if one could develop an improved low-temperature, low-voltage anodic bonding process, multiple fully-functional PCBs could be bonded with multiple glass wafers.
There are other techniques for fabricating multilayer or multi-wafer substrates. Unfortunately, these other fabrication processes require even higher temperatures than required to anodically bonding silicon and glass wafers. For example, low temperature co-fired ceramic (LTCC) processes, which are common in the semiconductor and telecommunication industries, require temperatures in the range of about 850° C.